1. Field of the Invention
The present invention relates to a transmission circuit and a transmission method of using the transmission circuit, and more particularly relates to a transmission circuit to be connected to a plurality of devices and a transmission method of using the transmission circuit.
2. Description of Related Art
In recent years, in association with the rapid advancement of technology, the integration density in an SiP (System in Package) becomes more and more higher. Even in a transmission circuit network system of the SiP device and a device different from the SiP device, the configuration of a higher density and a higher speed operation are advanced.
In a typical transmission circuit network, a tuning of a transmission circuit network is performed for realization of a desirable transmission. For example, the use of a termination resistor, the use of a damping resistor (series termination), the adjustment of a transmission line impedance, the adjustment of a transmission line length, and the like are carried out.
Here, the following limits are caused in the transmission circuit network system in a high density mounting, in such a way that DRAM is installed inside the SiP and further the DRAM is connected on PCB (Printed Circuit Board). That is, an in-SiP transmission line is in the mounting state of a very high density. Thus, there is no margin to perform the tuning, and it is difficult to tune a line serving as a transmission line. Also, a scheme of using the termination resistor leads to the increase in power consumption. Moreover, in case that a plurality of devices are connected and signals are transmitted to and received from each other, the transmission delays cannot be made equal between the plurality of devices. The temporal deviation caused due to this transmission delay results in severe constraint in the high speed transmission.
At first, a typical transmission circuit network having no distortion will be described as a comparison target with reference to FIGS. 1 and 2.
FIG. 1 is a circuit diagram showing a transmission circuit according to a conventional technique. The transmission circuit contains two transmission lines T12 and T13. The two transmission lines T12 and T13 are connected in series. A contact in which the two transmission lines T12 and T13 are connected is referred-to as a connection point N72. One tip of the transmission line T12 is referred to as a connection point N71. The other tip of the transmission line T13 is referred to as a connection point N73. Devices DEV1, DEV2 and DEV3 are connected to the three connection points N71, N72 and N73, respectively.
The two connection points N71 and N73 also serve as the two terminations of the transmission circuit. The two connection points N71 and N73 are connected through two termination resistors RT1 and RT2 to two termination power sources VT1 and VT2, respectively.
As a specific connection, the termination resistor RT1 is firstly connected between the termination power source VT1 and a connection point N71, and the device DEV1 is connected to the connection point N71. The transmission line T12 is connected between the connection point N71 and the connection point N72, and the device DEV2 is connected to the connection point N72. Also, a transmission line T23 is connected between the connection point N72 and the connection point N73, and the device DEV3 is connected to the connection point N73. Then, the termination resistor RT2 is connected between the connection point N73 and the termination power source VT2. Here, each of the devices DEV1, DEV2 and DEV3 is a device having a bidirectional interface that contains a driver and a receiver.
The operations of the transmission circuit in FIG. 1 will be described below. At first, each of the two transmission lines T12 and T23 is assumed to meet that a transmission line impedance is 50Ω and a transmission delay is 250 ps. Each of the resistance values of the two termination resistors RT1 and RT2 is also defined as 50Ω. As for the two termination power sources VT1 and VT2, each of the voltages is defined as 0 V.
In FIG. 1, it is supposed that a signal is outputted from a driver of the device DEV1 and transmitted to a receivers of the devices DEV2, DEV3. The voltage of the signal outputted from the device DEV1 is defined as 1 V. The output impedance is defined as 25Ω that is equal to a half of a transmission line impedance. The rising time of the output signal is defined as 200 ps. A terminal capacitance of the device is defined as 1 pF.
The transmission line viewed from the device DEV1 seems to be in a state that the termination resistor RT1 of 50Ω and the transmission line T12 of 50Ω are connected in parallel. In short, an equivalent impedance of the transmission line when viewed from the device DEV1 seems to be 25Ω. Thus, it results in the state matched to the output impedance of 25Ω.
At the time of the rising time, the output level becomes the level when 1 V is divided by 25Ω of the equivalent impedance of the line and 25Ω of the output impedance of the device DEV1. Then, its value becomes 0.5 V as shown by the following equation (1):1×25/(25+25)=0.5
It is supposed that the signal is transmitted through the transmission line. This signal is transmitted as a state that the transmission lines T12 and T13 are matched to 50Ω, and with the termination of the RT2, it is transmitted in a state that they are matched to 50Ω until the final end. In short, a reflection is not generated except deterioration caused by the terminal capacitances of the devices DEV1, DEV2 and DEV3.
The final DC level is induced from the resistance division between a synthetic resistance of 25Ω in which the termination resistors RT1 and RT2 of 50Ω are connected in parallel and the output impedance 25Ω of the device DEV1. Thus, the final level is 0.5 V.
The properties of the two connection points N72 and N73 in FIG. 1 will be described below. Similarly to the fact that the reflection is not generated in the waveform of the device DEV1, the properties of the two connection points N72 and N73 become the property as the elapse point in the signal transmission. In short, the properties of the two connection points N72 and N73 become the property in which the property of the connection point N71 is transmitted after the temporal elapse corresponding to the transmission delays of the transmission lines T12 and T13. In short, the first level and the final level are equal to 0.5 V. Even in the transmission, the impedance is always matched, and the distortion caused by the reflection is suppressed.
FIG. 2 is a transmission property graph when the transmission circuit in FIG. 1 operates. The horizontal axis indicates time, and its unit is a nano-second (ns). The vertical axis indicates the voltage of the output of the transmission circuit, and its unit is a volt (V).
Three waveforms W3N1, W3N2 and W3N3 correspond to the properties of the three connection points N71, N72 and N73, respectively. Thus, in the bus connection inside an electronic apparatus, it is important to suppress the reflection in the transmission circuit network in order to attain the data transmission of a high speed.
In relation to the foregoing descriptions, Japanese Patent Application Publication (JP-A-Heisei, 11-45138) discloses a technique according to a high speed bus circuit method. In the high speed bus circuit method, a plurality of integrated circuits are connected through resistors to transmission lines, respectively, and the resistors and the transmission lines are connected to be alternately installed, and the entire bus is formed in the shape of one loop. In this related art 1, “it is same to a configuration in which six resistors r12, r23, r34, r45, r56 and r61 are added to a transmission circuit in a second embodiment of the present invention” is described.
Also, “a resistor R25, since acting as the termination resistor, can suppress the reflection. That is, since it can be regarded to have the same potential as a ground and a power source from the viewpoint of AC, it operates as the termination resistor, and the generation of the reflection components can be suppressed” is described in the same specification.
From the foregoing descriptions, the best values of the circuit constants in the respective members are estimated as follows. That is, at first, transmission lines SL21, SL22, SL23, SL24, SL25 and SL26 have their transmission line impedances of 50Ω, and their transmission delays are 250 ps, Also, the resistance values of resistors R21, R22, R23, R24, R25 and R26 are equally 50Ω.
Here, it is assumed that a signal is outputted from a driver of a device IC25 and transmitted to devices IC21, IC22, IC23, IC24 and IC26. At this time, the output signal outputted from the device IC25 is assumed to have the voltage of 1 V. Also, the output impedance is assumed to be 50Ω. Moreover, the rising time of the output signal is assumed to be 200 ps, and the terminal capacitance of the device is assumed to be 1 pF.
At first, the waveform of a connection point N95 in FIG. 2 will be described. The transmission line viewed from the device IC25 seems to be in a situation that an anticlockwise path and a clockwise path are connected in parallel. Here, an anticlockwise path is a path oriented in the direction of the transmission line SL24 and the resistor R24. Also, the clockwise path is the path oriented in the direction of the resistor R25 and the transmission line SL25.
From the viewpoint of the device IC25, the two paths of the equivalent impedances when they are viewed from the device IC25 differ from each other. At first, the anticlockwise path oriented in the direction of the transmission line SL24 and the resistor R24, since the transmission line is forwardly located, it seems to be equivalently 50Ω. On the other hand, the clockwise path oriented in the direction of the resistor P,25 and the transmission line SL25 seems to be equivalently 100Ω since the resistor is forwardly located.
Thus, the synthetic equivalent impedance when they are viewed from the device IC21 is about 33.3Ω as represented by the following equation (2).(50×100)/(50+100)=33.3
Thus, the output level is a level obtained by dividing 1 V by using 33.3Ω of the equivalent impedance of the line and 50Ω of the output impedance of the IC21. Its value is 0.4 V as represented by the following equation (3):1×R/(50+R)=0.4Here,R=(50×100)/(50+100)
The changes in the respective connection points with regard to a signal voltage transmitted through the transmission lines are sequentially determined when the signal of 0.4 V is transmitted through the clockwise path and anticlockwise path in the transmission lines connected in the shape of a ring. In the transmission, the equivalent impedance of each connection point is 50Ω when “the transmission line is forwardly located and the resistor is backwardly located” and 100Ω when “the resistor is forwardly located and the transmission line is backwardly located”. This difference namely results in a mismatching. Thus, the transmission of the-signal causes the reflection and the attenuation to be repeatedly generated for each connection point. Moreover, the transmission lines are connected in the shape of the ring. Thus, with the overlapping with the reversely circulating signal, the property is also changed in correspondence to this overlapping.
The transmission circuit is ring-shaped, and it is not terminated. Thus, the final DC level is 1 V that is equal to an input signal. However, “the clockwise signal” and “the anticlockwise signal” and “the multiplex reflection” generated by the mismatching of each of the connection points are overlapped. Accordingly, as the result of the increase in the voltage, the 1 V is finally induced.
In the transmission circuit according to the related art 1, as the property of the connection point N95, the waveform of W4N5 in FIG. 4 is obtained. Similarly, waveforms W4N1, W4N2, W4N3, W4N4 and W4N6 in FIG. 4 correspond to the properties of connection points N91, N92, N93, N94 and N96, respectively. As evident from those waveforms, the distortion of the waveform caused due to the reflection signal is not suppressed. In addition, in the conventional technique, the transmission delays cannot be made equal. Thus, in the high speed transmission, the deviation between the transmission delays results in the severe constraint.
The technique disclosed in the related art 1 will be described below in further detail, in accordance with FIGS. 3 to 7. FIG. 3 is a circuit diagram of the transmission circuit in the conventional technique of the related art 1. Each of the ICs 21 to 26 is an IC that a driver and a receiver are built in. The SL21 to SL26 are the transmission lines on the printed circuit board through which the signal on the bus is transmitted. The R21 to R26 are the resistors.
The operation of the basic circuit in the conventional technique will be described below. At first, in the transmission of the data through the bus, the bus is driven by various integrated circuits (hereafter, referred to as ICs) that include a processor in which the driver and the receiver in any one of the ICs 21 to 26 connected to the bus is built in. The operations when the signal appearing in the bus at that time is received by the other IC are similar to the operations of the conventional example in FIG. 1. Also, all the receivers in the related art 1 are high in input impedance and are lightly affected with regard to the signal transmission, similarly to the conventional example. Thus, the waveform distortion in this portion is assumed to be able to be ignored.
FIG. 4 is a transmission property graph showing the transmission circuit in the related art 1. The feature in this transmission property graph lies in a design that the bus is loop-shaped and the respective resistors are inserted in series between the transmission lines through which the respective ICs are connected and one sides of the resistors are directly connected to the respective drivers and receivers without passing through the transmission lines. For example, a case in which the IC25 drives the bus and sends the signal is shown in FIG. 5 when the circuit is equivalently rewritten.
FIG. 5 is a circuit diagram showing the operation of the transmission circuit in the related art 1. In this circuit diagram, at the moment when the driver of the IC25 drives the bus, the left end of the transmission line SL24 located closest to the output and the left end of the transmission line SL25 through the resistor R25 serve as a load. Then, the anticlockwise signal transmission route whose start point is the left end of the transmission line SL24, as indicated by the dotted line arrow in FIG. 5, and the clockwise signal transmission route whose start point is the resistor R25 in the direction opposite to the dotted line arrow are configured. When the anticlockwise signal transmission route shown in FIG. 5 is further rewritten, the equivalent circuit shown in FIG. 6 is obtained.
FIGS. 6A and 6B are equivalent circuit diagrams corresponding to the transmission circuit in the related art 1. In this equivalent circuit diagram, the driver of the IC25 firstly drives the left end of the transmission line SL24. Then, the signal transmitted through the SL24 next arrives at the transmission line SL23 through the resistor R24. Moreover, the signal is transmitted in an order of the resistor R23, the transmission line SL22, the resistor R22, the transmission line SL21, the resistor R21, the transmission line SL26, the resistor R26, the transmission lines SL25 and R25. At the resistor R25, the element connected to the side opposite to the transmission line SL25 is the output of the signal source IC25 in FIG. 5.
However, in FIGS. 6A and 6B, a case when the output of the IC25 is “L” is equivalently indicated by a circuit 3 in FIG. 6A, and a case when the output of the IC25 is “H” is equivalently indicated by a circuit 4 in FIG. 6B. That is, when the output of the IC25 is “L”, the termination resistor R25 can be considered to be connected through a small impedance r to the ground. Also, when the output of the IC25 is “H”, it can be considered to be connected through the small impedance r to a voltage level VH at the time of the “H”. Thus, since the resistor R25 is terminated at the same voltage level as the output of the signal source IC25, the wasteful consumption current does not flow. Then, when the output impedance r of the IC25 is made sufficiently small, the resistor R25 acts as a termination resistor, and the reflection can be suppressed. That is, it can be regarded to have the same potentials as the ground and the power source in the AC manner. Therefore, it acts as the termination resistor, and the generation of the reflection component is suppressed. On the other hand, when the clockwise signal transmission line opposite to the dotted line arrow in FIG. 5 is further rewritten as the equivalent circuit, the circuit shown in FIG. 7 is obtained.
FIG. 7 is an equivalent circuit diagram corresponding to the transmission circuit in the related art 1. As evident from this equivalent circuit diagram, the resistor R25 connected to the output of the driver of the IC25 operates to decrease the reflection by acting as the transmission end resistor when the transmission line SL25 is driven. It should be noted that all of the resistors R21 to R26 inside this high speed bus have the same voltage level in the DC manner. Thus, the wasteful consumption current does not flow.
In order to attain the high speed data transmission in the bus connection inside the electronic apparatus, it is important to suppress reflections in the transmission circuit network. The technique disclosed in the related art 1 describes that as mentioned above, the reflection is suppressed and further the typical termination resistor is not used, which attains the suppression in the DC power.
However, in the technique of the related art 1, the reflection cannot be suppressed contrarily to the description. In the specific example in the technique of the related art 1, its property indicates the waveform shown in FIG. 4. A number of shelves caused by the multiple reflections are generated near a logical threshold. Thus, far from suppressing the reflection, actually, there is the large number of multiple reflections.